Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EASNEEDS
Project Goals
The growing requirements on the functional scope of electronic systems have given rise to complex systems on a single chip. The addition of further functionality, such as sensors or radio interfaces, is very cost-intensive, however. Three-dimensional, stacked electronic circuits (3D chips) open up new implementation options for such complex systems. They can be more compact, faster and more energy-efficient while allowing the integration of sensors, actuators or other components. Because existing tools and design methods are specialized for classic two-dimensional chips, the partners in the NEEDS project want to develop new design procedures. These should make it possible to analyze 3D chips with regard to their performance and costs and optimize them even before production.
Approach
The partners are investigating various steps of the circuit design process in which new possibilities and requirements arise from 3D integration. These include communication structures, placement of components in the stack (floorplanning), test concepts, manufacturing processes and the analysis of thermal effects in the stack. The results of the sub-disciplines enter into a hierarchical optimization process called design space exploration, which is intended to optimize the architecture of the chip stack with regard to production costs and performance. This design methodology should enable a holistic perspective of the 3D realization that is independent of the field of application. The results will be demonstrated on the basis of a design platform.
