The automotive radar industry is currently in a state of major upheaval due to the proliferation of autonomous driving, which requires 360° monitoring of the vehicle’s surroundings in a dynamic environment. As a result, radar sensors have to detect more than 1,000 objects simultaneously, classify them using imaging techniques, estimate their size and direction, and track them. Accordingly, more efficient and better integrated systems will require new technologies that have yet to be developed.

The specific technical challenge in this case is increasing sensor resolution in terms of range, speed, and angle. Another important property is the robustness of the radar sensor against interference from other sensors installed in the same vehicle or others. The goal of the ARAMID project is to create a chip incorporating innovative interference reduction and avoidance measures not currently available in a mass-manufactured product. This is especially crucial as the number of radar sensors in use can be expected to increase sharply in the future.

Finally, a radar sensor should not produce “ghost images” in the resulting radar image caused by reflections of the radar beam in the vehicle’s surroundings. Appropriate correlation between the radar image and a predicted image with extrapolated object movements can dramatically improve the quality of the radar image.

To obtain sufficient information for the radar demonstrator, a large number of measures are necessary. These include optimizing the range resolution, developing analog-to-digital converters that facilitate a higher sampling rate of range and speed data, and special algorithms and filters to enable plausibility checks of the radar image. Furthermore, AI algorithms are employed for object classification. The demonstrator is expected to be able to support software-based object classification with artificial intelligence. To this end, suitably powerful processors will be integrated into the chip.

Fraunhofer IIS/EAS is involved in two ways: First, by testing thermal interactions on the developed circuit; and second, with work on aging models and evaluation of IC reliability. This will help avoid failures due to electromigration, as well as unnecessarily oversized circuits.

The Fraunhofer division is also working on an assembly design kit for the semiconductor technology used in the chip. It is developing the first continuous process for the package design, using standard tools from circuit and PCB design.