There are many aspects to consider in microelectronics in order to ensure reasonable reliability for an application at reasonable expense. As part of the iREl40 project, various pieces of research were carried out in this area at Fraunhofer IIS/EAS.

At the system level of electronics, reliability is underpinned by wide-ranging mechanisms. The influence of individual effects is typically investigated in comprehensive FEM simulations, but these simulations are poorly suited to analyzing the interplay between different effects. There is therefore a need for more-efficient compact models. Researchers used the example of soldered joints, which experience mechanical loading due to vibration and stresses, to research and successfully apply such an approach based on radial base functions. This work laid the foundation for investigating other effects.

At the level of integrated circuits, reliability can be increased most effectively if it is considered as a design objective during development. This has been possible for years with the help of aging simulations in different design environments, but simulations of this kind are still rarely used because of the costs involved and the difficulty in interpreting some of the results. With this in mind, an add-on to commercial design tools has been developed at Fraunhofer IIS/EAS. The add-on uses technological information from the semiconductor manufacturer as well as loading scenarios from the user to determine the extent to which each transistor will degrade in a circuit. In a manner that will be familiar to designers, the results are visualized as an overlay onto the circuit diagram (schematic), providing users with low-threshold access to transistor reliability in their circuits.

Working in close coordination with various partners from the consortium, Fraunhofer IIS/EAS has therefore made key contributions toward future applications of European reliable electronics.